The present invention relates, in general, to the field of semiconductor integrated circuit devices. More particularly, the present invention relates to a switched capacitor charge sharing technique for integrated circuit devices enabling signal generation of disparate selected signal values.
Charge sharing techniques have previously been employed in integrated circuit designs in order to save operating power. A typical circuit example is one utilized in conjunction with dynamic random access memory (DRAM) array bitlines which are precharged to a level of VCC/2 then driven to VCC (supply voltage level) or VSS (circuit ground) for the bit line (BL) and complementary bit line bar (/BL or BLB) depending on the state of the previously stored data.
Other contemporary circuit examples include the use of three groups of logic gates operating at three different voltage ranges. In operation, one group will transition from VCC/3 to VSS, the second group from 2VCC/3 to VCC/3 and the third group from VCC to 2VCC/3. In this manner, these three groups of logic gates can charge share with their adjacent voltage range group, but conventional designs are constrained to operate in this manner. Stated another way, with current circuit techniques the low level of signal or circuit block A is set equal to the high level of the adjacent signal or circuit block B.
What is desired then, is the provision of a charge sharing technique that allows for selected signal, or operating, levels without concern for the number of circuit blocks used to share the charge. In other words, it would highly advantageous to provide, for example, two circuit blocks that can charge share with each other but have VCC/10 operating levels. That is, one signal or block could operate in the range of VCC to 0.9VCC while another signal or block operates between VSS to 0.1 VCC with the two signal generators charge sharing with each other.